human
Here exactly does a shift register do given the following:
I am working on the file "01_mex_shifty.ipynb".
The first task is:
MyHDL Function (module)
An introductory MyHDL tutorial presents a small example towards the begining of the post.  A MyHDL anatomy graphic (see below) is used to describe the parts of a MyHDL module.  Note, the nomenclature is a little odd here, in Python a module is a file and in MyHDL a module (typically sometimes called a component) is a Python function that describes a set of hardware behavior.  Hardware module is commonly used to name an HDL component in a digital circuit - the use has been propagated forward.
<center><figure>
<a href="https://www.flickr.com/photos/79765478@N08/14230879911" title="myhdl_module_anatomy by cfelton*, on Flickr"><img src="https://farm3.staticflickr.com/2932/14230879911_03ce54dcde_z.jpg" width="640" height="322" alt="myhdl_module_anatomy"></a>
<caption> MyHDL Module Anatomy </caption>
</figure></center>
A Shift Register
<!-- there is an assumption the user will know what a shift register is, these exercises are for people that know Verilog/VHDL.  Not teaching digital logic from scratch !! -->
What exactly does a shift register do?  In the exercise description section there is a link to a short video describing a shift register.  Basically, to generate a shift register all we really need is a description of what the expected behavior is.  In this case we have a parallel value, load_value, that will be serialized to a single bit, the following table shows the temporal behavior.  If we have an constrained integer with a maximum value of 256, the following will be the behavior:
Time | load | ival (d) | shift (b) | obit
-----+------+----------+-----------+-----
T0   | 1    |  32      | 0000_0000 | 0
T1   | 0    |  X       | 0010_0000 | 0
T2   | 0    |  X       | 0100_0000 | 0
T3   | 0    |  X       | 1000_0000 | 1
T4   | 0    |  X       | 0000_0001 | 0
T5   | 0    |  X       | 0000_0010 | 0

In the above table abbreviations are used for the Signals listed in the module.

ival: initial_value
shift: shiftreg
obit: output_bit

Exercise Description
This exercise is to implement the...
Can you write Python program for it?
assistant
#Here exactly does a shift register do.

def shifty(clock, reset, load, load_value, output_bit, initial_value=0):
    """
    Ports:
       load: input, load strobe, load the `load_value`
       load_value: input, the value to be loaded
       output_bit: output, The most significant 
       initial_value: internal shift registers initial value (value after reset)
    """
    assert isinstance(load_value.val, intbv)
    
    # the internal shift register will be the same sizes as the `load_value`
    shiftreg = Signal(intbv(initial_value, 
                            min=load_value.min, max=load_value.max))
    mask = shiftreg.max-1
    
    # non-working template
    @always_seq(clock.posedge, reset=reset)
    def beh():
        output_bit.next = shiftreg[0]
        
    # for monitoring, access outside this function
    shifty.shiftreg = shiftreg
    
    return beh